- 유창식 교수 | 혼성 신호 회로 설계, AI 시스템을 위한 메모리 설계
-
- 정보통신대학 - 반도체융합공학과
- 산학협력센터 7층 85797호실
- 031-290-7117
- https://sites.google.com/g.skku.edu/ssc-labskku/home
- changsik.yoo@skku.edu
- 학력 Education
-
- (Ph.D.) Seoul National University
- (M.S.) Seoul National University
- (B.S.) (Highest Honor) Seoul National University
- 약력/경력 Experience
-
- Executive VP, Samsung Electronics (2020-2025)
- Visiting Researcher, Samsung Electronics (2019-2020)
- Visiting Professor, Swiss Federal Institute of Technology (EPFL, Lausanne) (2018)
- Technical Advisor, DB HiTek, Seoul, Korea (2017)
- Co-Founder & CTO, SmartPHY Inc. Seoul, Korea (2010-2015)
- Senior Engineer, Silicon Image Inc. California, USA (2008-2009)
- Professor of Electronic Engineering, Hanyang University, Seoul, Korea (2002-2020)
- Senior Engineer, Samsung Electronics, Korea (1998-2002)
- Research Staff, Swiss Federal Institute of Technology (ETH, Zurich) (1998-1999)
- 관심분야 Research Interest
-
- 아날로그 및 혼성신호 회로 설계
- AI 시스템을 위한 메모리 설계
- 연구키워드 Research Keyword
-
- Analog and Mixed-Signal Circuits / Memory for AI Systems
- 논문 Journal Article
-
- A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM, IEEE Solid-State Circuits Letters, 2025
- An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier, IEEE J. Solid-State Circuits (JSSC), 2025
- A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration, IEEE J. Solid-State Circuits (JSSC), 2024
- A 4 ns settling time FVF-based fast LDO using bandwidth extension techniques for HBM3, IEEE J. Solid-State Circuits (JSSC), 2024
- An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM, IEEE Symp. VLSI Technology and Circuits (SOVC), 2024
- A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications, IEEE Asian Solid-State Circuits Conf. (ASSCC), 2023
- A 16-Gb/s/wire 4-wire short-haul transceiver with balanced single-ended signaling (BASES) in 28-nm CMOS, IEEE Trans. Circuits and Systems-II, 2023
- An 8b9b 77.44-Gb/s noise-immune spatial-delta coded transceiver for short-reach memory interfaces in 28-nm CMOS, IEEE Trans. Circuits and Systems-II, 2023
- A 12-Gb/s baud-rate clock and data recovery with 75% phase-detection probability by precoding and integration-hold-reset frontend, IEEE Trans. Circuits and Systems-II, 2023