Global Leading University
Analog & RF Circuit and System Research Center


박준은 교수 | 혼성회로 집적회로 설계
학력 Education
  • (Ph.D.) Electrical and Computer Engineering, Seoul National University, Korea (2017)
약력/경력 Experience
  • Assistant Professor, Chungnam National University (2020-2023)
  • BK Assistant Professor, Seoul National University (2018-2020)
관심분야 Research Interest
  • Power Management ICs
  • Processing In Memory (PIM)
  • Sensor Interfaces
  • Low-Power Circuits
  • Embedded Memories
  • Mixed-signal Circuit Modeling and Design Automation
연구키워드 Research Keyword
  • Analog Circuits / Mixed-Signal Circuits / Artificial Intelligent / Power Management / Sensor / CAD / Design Automation
논문 Journal Article
  • Y. -H. Hwang, J. Oh, W. -S. Choi, D. -K. Jeong and J. -E. Park, "A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns," in IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2236-2249, July 2022
  • Y. Song, J. Oh, S. -Y. Cho, D. -K. Jeong and J. -E. Park, "A Fast Droop-Recovery Event-Driven Digital LDO With Adaptive Linear/Binary Two-Step Search for Voltage Regulation in Advanced Memory," in IEEE Transactions on Power Electronics, vol. 37, no. 2, pp. 1189-1194, Feb. 2022
  • J. -E. Park, Y. -H. Hwang and D. -K. Jeong, "A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors," in IEEE Access, vol. 7, pp. 63686-63697, 2019
  • J. -E. Park, J. Park, Y. -H. Hwang, J. Oh and D. -K. Jeong, "A Noise-Immunity-Enhanced Analog Front-End for 36×64 Touch-Screen Controllers With 20- VPP Noise Tolerance at 100 kHz," in IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1497-1510, May 2019
  • J. -E. Park, Y. -H. Hwang and D. -K. Jeong, "A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 12, pp. 1417-1421, Dec. 2017
학술활동 Conference Paper
  • J. -E. Park, J. Hwang, J. Oh and D. -K. Jeong, "32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 492-494
  • J. -E. Park and D. -K. Jeong, "A Fully Integrated 700mA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit," 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2018, pp. 231-232
  • J. -E. Park, J. Park, Y. -H. Hwang, J. Oh and D. -K. Jeong, "11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016, pp. 210-211
수상 Honors / Awards
  • DOYEON Paper Award (2016)
  • Humantech Paper Award (2016)