- 이우근 교수 | 저전력 집적회로시스템
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- 반도체융합공학과
- 반도체관 6층 400616호
- 031-290-7116
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- wrhee@skku.edu
- 학력 Education
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- (Ph.D.) University of Illinois, Urbana-Champaign, IL, USA, 2001
- (M.S.) University of California, Los Angeles, CA, USA, 1993
- (B.S.) Seoul National University, Korea, 1991
- 약력/경력 Experience
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- IEEE Fellow
- Adjunct Chair Professor, Tsinghua University, 2025
- Professor, Tsinghua University, 2006-2025
- Research Staff Member, IBM T.J. Watson Research Center, 2001-2006
- Principal Engineer, Conexant Systems (now Skyworks), 1997-2001
- 관심분야 Research Interest
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- Energy-efficient short-range transceivers
- High-speed wireless/wireline interfaces
- Low-noise clock/frequency generation
- Low-power mixed-signal circuits & systems
- 연구키워드 Research Keyword
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- Analog/RF/AI/IoT
- 논문 Journal Article
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- L. Feng, Q. Liao, L. Kuang, J. Zhao, W. Rhee, and Z. Wang, “A 0.6-V fully-integrated BLE transmitter in 65-nm CMOS using a common-mode-ripple-cancelled hybrid PLL and a duty-cycle-controlled class-E/F2 PA achieving 25% system efficiency at 0 dBm,” IEEE Journal of Solid-State Circuits, Early Access, 2025.
- Y. Nie, W. Rhee, and Z. Wang, “A 27.9-mW 802.15.4/4z 1T2R transceiver with FIR-embedded quadrature hybrid correlation and AoA localization,” IEEE Journal of Solid-State Circuits, Early Access, 2025.
- X. Ji, J. Zhao, W. Rhee, and Z. Wang, “A polar phase-tracking receiver with two-point injection technique,” IEEE Journal of Solid-State Circuits, no. 5, vol. 60, pp. 1529-1540, May 2025.
- L. Feng, X. Ji, L. Kuang, Q. Liao, S. Han, J. Zhao, W. Rhee, and Z. Wang, “An ultra-low-voltage bias-current-free fractional-N hybrid PLL with voltage-mode phase detection and interpolation,” IEEE Journal of Solid-State Circuits, no. 1, vol. 60, pp. 85-98, Jan. 2025.
- Y. Nie, W. Rhee, and Z. Wang, “An IEEE 802.15.4/4z coherent quadrature hybrid correlation UWB receiver in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 59, pp. 2378-2389, Aug. 2024.
- B. Zhou, Y. Li, Z. Wang, C. Wang, W. Rhee, and Z. Wang, “A low-complexity FM-UWB transmitter with digital reuse and analog stacking,” IEEE Journal of Solid-State Circuits. vol. 59, pp. 2121-2132, July 2024.
- B. Wang, W. Rhee, and Z. Wang, “A 65-nm sub-10-mW communication/ranging quadrature uncertain-IF IR-UWB transceiver with twin-OOK modulation,” IEEE Journal of Solid-State Circuits. vol. 59, pp. 1656-1667, June 2024.
- L. Feng, W. Rhee, and Z. Wang, “A DTC-free fractional-N BBPLL with FIR-embedded injection-locked-oscillator-based phase-domain lowpass filter,” IEEE Journal of Solid-State Circuits. vol. 59, pp. 728-739, Mar. 2024.
- 저서 Publications
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- W. Rhee and Z. Yu, "Phase-Locked Loops: System Perspectives and Circuit Design Aspects," Wiley-IEEE Press, 2024.
- 특허 / 지적재산권 Patent / Intellectual Property
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- 수신기, 이의 동작 방법, 및 이를 포함하는 빔포밍 레이더 시스템. 10-2206739. 202101. 대한민국
- 듀얼 대역 통과 필터를 이용한 초광대역 장치 및 방법. 10-2051555. 201911.
- 가우시안 펄스 생성 장치 및 방법 그리고 가우시안 펼스를 생성하는 초광대역 통신 장치. 10-1954659. 202101. 대한민국
- 그 외 특허 24건. 미국
- 학술활동 Conference Paper
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- L. Lin, B. Wang, L. Kuang, W. Rhee, and Z. Wang, “A 1.8Gb/s 8GHz PSK-UWB transceiver with extended PPM/PWM modulation and embedded carrier spreading,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2025
- L. Feng, X. Ji, Q. Liao, L. Kuang, Y. Nie, J. Zhao, W. Rhee, and Z. Wang, “A 0.5V 0.55mm2 bias-current-free BLE transceiver with 1-bit delay-based demodulation for energy-harvesting IoT applications,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2025
- L. Feng, Q. Liao, L. Kuang, J. Zhao, W. Rhee, and Z. Wang, “A 0.6V fully-integrated BLE transmitter in 65nm CMOS using a common-mode-ripple-cancelled hybrid PLL and a duty-cycle-controlled Class-E/F2PA achieving 25% system efficiency at 0dBm” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2024
- X. Ji, J. Zhao, W. Rhee, and Z. Wang, “A 2.3nJ/b 32-APSK polar phase-tracking receiver with two-point injection technique,” accepted for Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2024
- L. Feng, X. Ji, L. Kuang, Q. Liao, S. Han, J. Zhao, W. Rhee, and Z. Wang, “A 0.45V 0.72mW 2.4GHz bias-current-free fractional-N hybrid PLL using a voltage-mode phase interpolator in 28nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024